Architecture for modular computer system in which one of the modules is dedicated to user-interface task

ABSTRACT

Very large amounts of data may be handled by the user interface of computers. The main processor is thus permanently overloaded, so that the computing power available for the actual application is sharply reduced in a manner that cannot be predicted without limiting the user requests. A new computer architecture is disclosed which allows a higher and more exactly predictable computing power to be achieved. In order to make the rest of the system independent from the user interface, the computer is subdivided in such a way that a first module (part 1) takes over the display and operation tasks of the user interface, a second module (part 2) takes over the processing of the application programs without their user interface, and a third module (part 3) takes over the remaining functional units. All modules have their own internal data paths. An interface between the first and second modules support the exchange of messages and data without affecting the independent processes in the first and second modules. The first and second modules have their own access paths to common devices located in the third module.

BACKGROUND OF THE INVENTION

Large amounts of data are handled by the user interface of computers.Data take up a considerable quantity of the computer's throughout,because on one hand the resolution of imaging systems is increasingconstantly and new applications such as animation and desktop videorequire high data transfer rates for structured or unstructuredgraphics, and on the other hand, with the constantly growing complexityof operating structures, shorter response times are being demanded frominter-active systems.

It is an established fact that not only the main processor in thecomputer but also, if necessary, additional passive or active componentsare used in order to generate the presentations made accessible to ahuman being by the imaging system (see: Foley, van Dam, Feiner, Hughes,"Computer Graphics, Principles, and Practice", 2nd edition,Addison-Wesley Publishing Company, Reading, Mass., ISBN 0-201-12110-7,and in the following especially EP 0350911 A2 for a service processor).

Present-day systems do not take account in their structures of theextreme demands that have to be met in order to achieve the operationalfunctionality of the user interface, nor the huge quantities of datathat have to be imported from or exported to a point outside thegraphics sub-system and the main processor in a very short time, e.g.from a mass storage device or an input/output interface. For instance,the image memory of a system that strives to attain a resolution of1600×1200 pixels with a colour depth of 32 bits per pixel will take upabout 7.5 MB. For an animation sequence running at 25 images per second,some 187 MB/second of new data will have to be imported into this memoryto recreate the image displayed. If an image repeat rate of 100 Hz isthe aim, however, 750 MB/s have to be read from this memory anddisplayed simultaneously.

This leads a severe overloading of the part of the computer installationthat is supposed to be working on an actual application, meaningcalculating and retaining the data and so forth. The performance of thispart of the computer is severely affected both by the heavy load placedon its data paths for transporting the data to and from the graphicssub-system, which can cause a blockage of the main processor or othersubordinate units (see also EP 0350911 A2 as an example of amulti-processor system in which the shared main memory of thisclose-coupled multi-processor system is described as the principle`bottleneck`), and,by the frequent interruptions suffered by the workingprocedure for the purpose of reacting instantly to an input from theuser or for maintaining the actuality of the presentation. Moreover,with these kinds of architecture it is not possible to forecast theirperformance without limiting the availability of the system for userqueries (see EP 0350911 A2, if the system support processor is occupiedwith handling interrupts, semaphores, etc.).

SUMMARY OF THE INVENTION

The present invention is thus based on the task of reducing the load onthe parts of the computer handling the actual application caused byimplementing the user interface for presentation and function, therebyin order to achieve more efficient computers with which, even if theirfamiliar components are retained and even despite ever more stringentdemands on the quality of the user interface, it will be possiblegreatly to increase the capacity available for the application and toachieve a good level of predictability.

According to the method of the invention the present solution consistsof the architecture for a computer with a user interface along the linesof claim 1, characterised by:

a) the components of the computer being divided into three parts in sucha way that one of them, Part 1 (101), mainly takes over the function ofproviding the user interface in presentation and function; another, Part2 (102), mainly operates the application programs divorced from theiruser interface and the operating programs needed for it; and the third,Part 3, takes charge of the remaining components (107, 108, 109, 110) ofthe computer; the parts not necessarily being physically separated fromone another, as it is preferable to strive for a single unit ofequipment,

b) Parts 1, 2, and 3 possessing their own separate data paths for theirinternal tasks,

c) a software and hardware interface (103) existing between Part 1 (101)and Part 2 (102), which supports the exchange of messages and datawithout creating a direct, permanent connection which affects theindependent running of the processes in Parts 1 and 2,

d) Part 1 and Part 2 each having their own access path (105, 106) tojointly used additional components in Part 3.

With regard to the additional features of the invention, reference ismade to the sub-claims.

The advantages attainable with this invention consist mainly of theeffects described in the following summary:

The separation (see claims 1a and 1b) of Part 1, which handles the userinterface, from Part 2, which handles the actual application (forinstance: making calculations, administering data, or making logicalcombinations), leads to the clear uncoupling of these areas and thus toa far more efficient computer. For instance, a change of context by theprocessor, as is customary with present-day architecture, can in manycases be avoided completely.

Parts 1 and 2 can be optimized much more effectively for their actualtasks (see claims 2, 3, 5, 6, and 7) than is possible with any system inwhich both tasks are handled by one and the same part, for instance, asingle processing unit consisting of a processor, a memory, and aninput/output.

Part 1's and Part 2's own access paths to the shared components in Part3 (see claims 1a, 1d, 2, 3, 5, 8, and 9) increase the potentialperformance of the system, because for instance, while Part 1 is makinguse of its access to a component in Part 3 (e.g. in order to loadanimation data from a mass storage device or a network), Part 2 cancontinue to work without interruption on its local data paths (seeclaims 1b, 1c, 3, and 7). In the customary system, this kind of accesseither has to be handled by the central processor itself, for instance,by reading data from the mass storage device and passing it on to thegraphics card, or at least a bus system in the central processor has tobe used which then more or less blocks it.

If the invention is implemented with suitable synchronisation equipmentfor access by Parts 1 and 2 to the jointly used-components in Part 3(see claims 1d, 8, and 9), it can be guaranteed that even if maximumthroughput is being fully utilized, the part that has the highestpriority at any given moment will have access with only a minimum delay.Any necessary synchronisation can, for instance, be provided via thesoftware and hardware interface between Parts 1 and 2 (see claims 1c and4) or by a connection between the components in Parts 1 and 2responsible for access (see claims 8 and 9).

The structural unification of the part of a computer responsible for thepresentation and that responsible for the operational functionality ofthe user interface (see: claim 1a) permits extensive optimization suchas would not be possible if these components were separated. In thecustomary architectures today, although the presentation is admittedlyaccelerated by it's own processors, handling the response to the user(meaning the functionality of the user interface) still always has to bethe responsibility of the central processor, which therefore has tointerrupt whatever calculations are being carried out and thus has tostop them for the necessary length of time. For instance, the objectoriented structure of modern user interfaces can be better representedwith the new architecture as described in claim 1 on the computer'sarchitecture because any object of the user interface will generallyconsist of presentation and function, which are handled here by one andthe same unit (see claims 1a, 1b, 2, and 6).

Data retention becomes easier because it is possible to do, at preciselythat place where the graphic presentation is being made, the correlationof a co-ordination point on the screen surface (meaning, for instance,the position of a pointer) to the individual objects or structures ofthe user interface (see claims 1a, 1b, 2, and 6). For instance, thecalculation of the mutual covers of such objects now only has to be doneonce.

The structure that is defined by the architecture in the computer issimilar to the client/server software structure of modern operatingsystem/user interface combinations. A division with message exchange anddata transfer is provided here as well (see claims 1c and 4). This willfacilitate a particularly simple adaptation of such systems to the newarchitecture. Older systems can likewise be transformed by appropriatemeasures (see claim 1c), for instance by the provision of amultiple-access or dual ported memory.

Unlike genuine client/server structures, as are to be found for instancein so-called X-terminals, all the advantages are retained in thisarchitecture of decentralized hardware with its own computing capacityfor applications (see claims 5, 6, and 7). Moreover, and in contrast tothe possibilities described in Patent EP 401803 and elsewhere (thecombination of several separate computer units), it is also possible tomake use of techniques which are only feasible when the connections arekept short, meaning when they are all inside the one computer (seeclaims 1a, 1c, 4, 8, and 9).

A distinguishing feature of the architecture is a clear modularisation,even if in actual practice it may not be visible in a physical orspatial form (see claims 1a, 1b, 1c, 1d, and 10), and this makes itsimple to exchange parts in order to modify or increase the output or touse various different processors (see claims 2, 3, 6, and 7) orcomponents in the three parts.

It is easy to see that the advantages of modularization listed here andthe similarity of this architecture to modern operating systems makes itpossible to use this architecture independently of the design of thepart-components, and that this makes it suitable for use with all knownsystems with a number of different processors and different operatingsystem/user interface combinations (see claims 1a, 1c, 2, and 3).

BRIEF DESCRIPTION OF THE DRAWINGS

The following text will now describe three possible examples of theimplementation of the invention in practice, with reference to thedrawing, in which:

FIG. 1 schematically shows an example of the architecture of a computer.

FIG. 2 illustrates possible designs of Parts 1 and 2.

FIG. 3 illustrates possible design of Part 1.

The abbreviations used in the drawings are explained in the text.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

There now follows an explanation of the invention on the basis of thedrawings of three implementation examples in terms of the constructionand, where appropriate, of the way in which this invention works.

The details of the possible implementations such as special processors,bus systems, etc., are intended to serve only to communicate a betterunderstanding of the present invention. It will be clear to the readerthat the invention can be put into practice even without these specialdetails. Schematic presentations are used in the drawings in order notto burden the invention with unnecessary details.

FIG. 1 shows a schematic example of the implementation of thearchitecture. A Processing Unit One 101 representing Part 1, which forinstance could consist of a microprocessor with memory and peripheralinterfaces (see claim 2), has an interface 103 for messages and dataconnecting it to another part, Processing Unit Two 102 likewiserepresenting Part 2 (see claims 1a and 1c). The separated internal bussystems of the two processing units are not illustrated (see claim 1b).

Part 3 is shown in this example as the additional units 107 (massstorage), 108 (network or remote data transmission) and 109(input/output control, I/O), the periphery bus connecting thesecomponents 104 and the external peripherals 110 (printer, scanner, etc.)connected to I/O 109 (see claim 1a).

Processing Unit One 101 is connected via its own access path 105 to theperipheral bus 104 in Part 3 (see claim 1d). Accordingly, ProcessingUnit Two 102 is connected with its own access path 106 to the peripheralbus 104 and thus to the jointly used components 107, 108, 109, and 110in Part 3. The mutual terminal arrangements of the peripheral bus 104 bythe Processing Units One 101 and Two 102 can be made, for instance, by acollision-detection process, similar to that used in the Ethernet.

The type of access to the individual components 107, 108, 109, and 110using the peripheral bus 104, and the selection of the components, areshown only by way of an example and do not represent any inherentcharacteristics of the present invention. For instance, it would beequally possible to use a crossbar switch, which would permit thesimultaneous access of the processing units representing Parts 1 and 2to the components of Part 3 so long as the component groups itcontrolled were disjunctive.

The design of Processing Units One 101 and Two 102, which representParts 1 and 2 in claim 1, is likewise only an example. Another, moreadvanced, design is shown in FIG. 2. The processing units in thisdrawing are shown as 201 (Processing Unit One, PE1), and 202 (ProcessingUnit Two, PE2), as they merely represent a further possible design (seeclaims 1a, 2, 3, 6, and 7).

PE1 201 is connected via an access path of its own 207, which in thiscase could for instance be implemented in the form of an SCSI or an IEEEbus, with a peripheral bus 206 (see claim 1d). PE2 202 could, but neednot necessarily, be connected in the same fashion via 208 to 206. Let anSCSI or an IEEE bus be assumed as the connecting equipment 209(periphery bus control unit One, PBK1) and 213 (periphery bus controlunit Two, PBK2). The connection 203 for message interchange between PBK1and PBK2 is optional (see claims 8 and 9), but could for instance bemade through an additional connection between the host adapters or byspecial protocols on the peripheral bus 206 or via a roundabout routevia the access paths 204 for data or 205 for messages.

PBK1 209 is furthermore connected to 210 (memory One, S1), which wouldbe feasible via a direct memory access (DMA) to memory S1, and to 211(extension unit 1, EE1). EE1 211 (see claim 6) can, for instance,contain adapters for image output 217 (image output device BAG) or forthe connection to input devices 218 (input device EG). Also, in additionto the connection with PBK1 209 already mentioned, it has one connectionto S1 210 and another to processor 212 (processor One P1). The lattercould be a microprocessor adapted for graphics. This has an additionalinternal connection inside PEI 201 with S1 210. This will make theinternal, independent bus systems in PE1 201 representing Part 1 clear(see claim 1b).

The internal construction of PE2 202 is similar in all relevantrespects. PBK2 213 is connected to S2 214 (memory Two, S2) and EE2 215(extension unit 2, EE2), which in this example could consist of amathematical co-processor (see claim 7). S2 214 has connections to PBK2213, EE2 215, and the processor P2 216, which in turn has contact withEE2 215. P2 216 could be any suitable microprocessor. It emerges at thispoint that the present invention can be readily adapted to fit in withexisting architectures by letting the old architecture take the place ofPart 2 (in this case PE2 202) which is augmented in a suitable manner,for instance using one of the methods described here, by a Part 1 (inthis case PE1 201) and connected to it. In this way, it should bepossible to use components from the existing architecture, e.g. agraphics card in PE1 201.

Connection 204, for handling data between S1 210 and S2 214, could takethe form of DMA transfer that may be initiated by processors P1 212 andP2 216. Connection 205, for handling messages, could take the form ofinterrupt lines by means of which the processors would inform oneanother of events which could if necessary be accompanied by a transferon 204. Alternatively, queues could be implemented in hardware (as FIFOmemories, for instance) (see claims 1c and 4).

If connections 203, 204, and 205 have been clearly defined, PE1 201could also for instance be replaced if need be, even at a later date, bythe variant PE1 301 shown in FIG. 3. The reverse also applies, ofcourse, for any other implementation of PE2 202. This makes the possiblemodular concept visible (see claim 10).

PE1 301 as shown in FIG. 3 has the same basic structure as PE1 201. Acorrelation results, in respect of the basic function: P1 302corresponds to P1 212, but in this case should instead be implemented asa universal processor because the graphics functions, as will beexplained later, can be taken on by other components. It has aconnection with S1 303, corresponding to S1 210, but can perhaps alsohave different key data. This in turn is connected to PBK1 304, whichcorresponds to PBK1 209. P1 302, S1 303, and PBK1 304 each has one ormore than one connection to the remainder of PE1 301, which is thecounterpart to EE1 211. Let the following components of EE1 211 bepresented here in detail by way of examples: a digital signal processor(DSP) 308 connected to S1 303 and with interfaces to 312 (audio inputdevice AEG) and 313 (audio output device AAG); an input processing unitEPE 307, which has an interface to one or more than one input devices EG311; and a video processing unit (VPE) 306 which on the one hand has aninterface connected to 309 (image output device BAG) and anotherconnected to 310 (image input device BEG) but on the other hand also hasaccess to a scalable number of image processing units (BPE1, BPE2, BPE3,. . . ) 350, 351, 352 . . . The BPE's could take the form of smallmodules composed of a simple graphics processor, possibly combined witha BITBLT function, and a part of the image memory. They generate inparallel the presentation which is read from VPE 306 and issued as avideo signal, or alternatively arrives as a video signal at VPE 306,where it is converted and distributed to the BPE's. The BPE's areconnected, individually or in groups, with compression/decompressionunits (KDE1, KDE2, . . . ) 330, 331 . . . which send data streams to andfrom PBK1 304 and the various different KDE's, converting them inwhichever way is required.

PBK1 304 can of course, for instance, consist of a number of parallelaccess units in order to attain a greater band-width.

All these components are controlled by a configuration and message bus305, through which the processor P1 302 coordinates everything.Interrupt signals and very small quantities of data, such as a singlecharacter of the keyboard, can also be transmitted via this bus (seeclaims 1a, 2, and 6).

The possible further access paths of their own which PE1 or PE2 mighthave to their own components in Part 3 have not been illustrated. Thesemight for instance consist of a modem connected via an interfaceallocated exclusively to PE2, or something similar (see claim 5).

I claim:
 1. An improved computer system with a user interface containinga number of processing units using separate internal bus systems, andequipment for tranferring data and messages, and software programs for asystem-wide administration of the user interface, wherein theimprovement comprises:a) the hardware and software components of thecomputer system are divided into first, second and third modules, saidfirst module providing the user interface a presentation and afunction;said second module operates application programs and does notcontain any of the operating programs and computer components needed forthe user interface; said third module takes charge of remainingcomponents including at least a mass storage through a connectingstructure which is suitable for providing access to these components;and said three modules are implemented as a single unit of equipmentapart from any external peripheral components; b) said modules eachpossess their own data paths for handling internal tasks, which datapaths are separate from those of the other modules; c) a software andhardware interface exists in the unit of equipment between said firstand second modules, which interface supports exchange of messages anddata without creating a direct, permanent connection affectingindependent running of processes in said first and second modules; andd) said first and second modules each has its own, direct connectionpath to jointly used additional components in said third module.
 2. Thecomputer system of claim 1, wherein said first module is implemented byat least a first processor with a first memory and a first accesscomponent, which first access component is connected to those componentsin said third module which are to be jointly used with said secondmodule.
 3. The computer system of claim 1, wherein said second module isimplemented by at least a second processor with a second memory and asecond access component, which second access component is connected tothose components in said third module which are to be jointly used withsaid first module.
 4. The computer system of claim 1, wherein theinterface between said first module and said second module provides anefficient exchange of data and messages through a use of interruptsignals and queues.
 5. The computer system of claim 1, whereinadditional access paths are exclusively designated for said first moduleand said second module to connect to those components in said thirdmodule which are allocated exclusively to them.
 6. The computer systemof claim 1, wherein a first additional specific equipment within saidfirst module supports any relevant functions, including accelerating agraphics assembly, and supporting various input/output devices, localmass storage and compression/decompression of data.
 7. The computersystem of claim 1, wherein a second additional specific equipment withinsaid second module supports various functions, including acceleratingmathematical functions, data retaining functions, phonetic search incomplete texts, and local mass storage.
 8. The computer system of claim1, wherein a connection exists between a first and a second accesscomponents respectively in said first and second modules, which accesscomponents facilitate access to jointly used components in said thirdmodule, which connection handles a collision by priority control on anyjointly used data paths.
 9. The computer system of claim 8, wherein theconnection is implemented in the form of priority control usingdynamically changeable priorities, enabling priorities to be changed forsaid first module or said second module compared to a respective baseconfigurations.
 10. The computer system of claim 1, wherein said threemodules are implemented as a modular design in which hardware andsoftware interfaces are designed to support various differentconfigurations and a retro-fitting facility to meet changingrequirements.
 11. A computer system, comprising:a first module having afirst bus system and a first processing unit, the first moduleperforming user-interface tasks; a second module located adjacent thefirst module, the second module having a second bus system and a secondprocessing unit, the second module executing application programs butperforming no user-interface tasks; an interface connecting the firstmodule and the second module to transfer data and messages between themodules; a peripheral bus connecting the first module via a first accesspath and the second module via a second access path; and a third modulehaving at least one additional unit that is connected to the peripheralbus, said at least one additional unit including a mass storage.
 12. Thecomputer system of claim 11, wherein the first module furthercomprises:a first memory and a first extension unit, the first memoryand the first extension unit being connected to one another and to thefirst processing unit so as to form a loop; and a first peripheral buscontrol unit connected to the first memory, the first extension unit andthe first access path.
 13. The computer system of claim 11, wherein thesecond module further comprises:a second memory and a second extensionunit, the second memory and the second extension unit being connected toone another and to the second processing unit so as to form a loop; anda second peripheral bus control unit connected to the second memory, thesecond extension unit and the second access path.
 14. The computersystem of claim 11, wherein the interface comprises a priorityinterface, a data interface and an interrupt interface.
 15. The computersystem of claim 14, wherein the priority interface is connected betweenthe first peripheral bus control and the second peripheral bus controlunit, the priority interface providing priority of accessing the thirdmodule by one of the first module and the second module.
 16. Thecomputer system of claim 15, wherein the priority interface providesdynamically changeable priorities depending on a base configuration ofthe first module and the second module.
 17. The computer system of claim11, wherein the at least one additional unit of the third module furthercomprises a network transmission unit connected to the peripheral busand an input/output unit connected to the peripheral bus.
 18. Thecomputer system of claim 17, further comprising an accessory unitconnected to the input/output unit.
 19. The computer system of claim 11,wherein the interface connecting the first module and the second modulecomprises at least one interrupt line that is not part of the peripheralbus.
 20. The computer system of claim 11, wherein the first modulefurther comprises a first memory and second module further comprises asecond memory, and wherein the interface connecting the first module andthe second module comprises means for transferring data between thefirst and second modules by DMA transfer.
 21. The computer system ofclaim 11, wherein the first module further comprises means for receivinginput data and supplying output data without using the peripheral bus.22. The computer system of claim 1, wherein the unit of equipment isitself modular in design.
 23. The computer system of claim 1, whereinthe remaining components of the third component further comprises anetwork/remote data transmission unit, an input/output interface, and anaccessory unit.